No.6（2011）2.Development of a real-time task tracer IP based on bus snooping methods

Yuji Takeda, Tadashi Okabe, Masashi Nakamura, Ken Sato

  Recently, the use of RTOS is advanced in a multi-core processor on FPGA/SoC, and to watch the task transitions is important when confirming dead-lock conditions and operations of real-time processing. However, the conventional methods which use software hook processes or processor specific hardware, i.e. the ICE, are not suitable for lengthy real-time monitoring without processor loading. Then, we have developed a task tracer IP to extract only task transitions by snooping a general-purpose bus of FPGA/SoC. This IP consists of several taps and a master, and the selectivity of communication I/F that transmits the trace data and the core scalability are improved. Moreover, it can compress the trace data through difference operations and variable length coding. A 46.3% reduction in traffic was confirmed as a result of actually tracing the TCB access by the TOPPERS kernel.
 

Keywords
FPGA/SoC, multi-core processor, RTOS (Real-Time OS), task trace, data compression

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